Area Efficient Architecture for Network on Chip based Router
This work consists of FPGA based design of reconfigurable router for NoC applications using VHDL. The router designed in this proposed session has four channels (namely, east, west, north and south) and a crossbar switch each consist FIFO buffers and multiplexers. FIFO buffers are used to store the data and multiplexers are used to control the input and output of the data. Firstly, south channel is designed which includes the design of FIFO and multiplexers. After that, the switch, arbiter and crossbar will design. All these designed channels, FIFO buffers, multiplexers and crossbar switches are integrated to form the complete router architecture. The proposed design is simulated using Modelsim and the RTL view is obtained using Xilinx ISE 13.4. Xilinx SPARTAN-6 FPGAs are used for synthesis of proposed design. Fixed priority arbiter is used to reduce the area of the proposed reconfigurable router.