Implementation of Random Number Generator in FPGA
A pseudo random number generator (PRNG) is also known as a deterministic random bit generator(DRBG). It is an algorithm which generates a sequence of random numbers. This paper presents an implementation of pseudo random number generator. The design is specified in VHDL and is implemented on altera FPGA device. It is based on the Residue Number System (RNS). It gives us the way to design a very fast circuit. This paper presents design and implementation of a pseudo-random number generator which is based on Blum Blum Shub, XOR Shift, Fibonacci series and Galois LFSR methods. We have demonstrate that how the introduction of application specificity in the architecture can deliver huge performance in terms of area and speed. The design is specified in VHDL and is analyzed on altera FPGA parameter. Which has given us higher throughput and also the parameter like area, propagation delay and power requirement.